Walk-in-interview 2017 for Project Associate, Lab Engineer at National Institute of Technology Delhi (NIT Delhi)
National Institute of Technology Delhi
Project Associate, Lab Engineer
2
23-07-2017
Walk-in-Interview will be held on 23rd July 2017 at 11:00 AM at Room No. 301, NIT Delhi A-7, Institutional Area, Nareal 110040, Delhi. INDIA. Project Associate Job Location: Delhi Last Date: 23rd July 2017 Number of Vacancy: 1 Posts
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Project Associate
Educational Qualification:B.Tech in Electronics and Communication Engineering (ECE) with minimum CGPA of 6.5 and having working experience in VLSI related software. Desirable: Working knowledge in UNIX/MATLAB/scripting, Cadence, Mentor graphics, Synopsys TCADetc.
Pay Scale:As Per Rules
Age Limit:As Per Rules
Last Date:23rd July 2017
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Lab Engineer
Educational Qualification: B.E. / B. Tech. in Electronics or Electronics & Communication or Computer Science or Electrical Engineering, with a minimum CGPA of 6.5 or minimum 60 % marks, having a working knowledge on Windows, Linux and VLSI Software tools. Desirable: M.E. / M. Tech. in VLSI Design or Microelectronics or equivalent. Working knowledge of VLSI CAD tools like Cadance/ Mentor/ Magma/ Tanner/ Xilinx & Experience in Linux system administration.
Pay Scale:As Per Rules
Age Limit:As Per Rules
Last Date:23rd July 2017
Delhi , India
Engineering jobs
Applicants must report at least one hour before the commencement of interview time with followings: A cover letter addressed to following: To The Chief Investigator, SMDP C2SD Programme National Institute of Technology Delhi. Date for Walk-in-Interview: July 23, 2017 11:00 AM Onwards Venue: Room No. 301
Download Official Notification.
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